1. Field
Exemplary embodiments of the present invention relate to a semiconductor design technology, and more particularly, to a semiconductor memory device including a redundancy circuit for outputting repair address information when a repair operation is performed, and a fuse circuit.
2. Description of the Related Art
As high density integration for semiconductor memory devices is advanced, the number of memory cells and signal lines included in a single semiconductor memory device is increased. Accordingly, the critical dimensions of internal circuits becomes narrower and the size of the memory cells is reduced because the semiconductor memory devices are integrated within a limited space. If even one memory cell in a semiconductor memory device has a defect, the entire device has to be discarded because it does not perform as required. As process technology for semiconductor memory devices develops, defects occur stochastically in only a small number of memory cells. To discard the entire semiconductor memory device due to a small number of defective memory cells is very inefficient in terms of the yield.
Accordingly, redundancy memory cells are included in a semiconductor memory device along with normal memory cells. When a defect occurs in a normal memory cell, the normal memory cell is replaced with a redundancy memory cell. A redundancy circuit may indicate that a normal memory cell has been replaced with a redundancy memory cell due to a defect in the normal memory cell. The redundancy circuit includes a plurality of fuses in which defective memory cell address information is programmed.
An array e-fuse (ARE) is a grouping of electrical fuses in an array. The redundancy circuit performs a boot-up operation for sequentially reading defective address information programmed into the ARE and storing the read defective address information in a latch.
FIG. 1 is a block diagram illustrating a known redundancy circuits included in a semiconductor memory device.
Referring to FIG. 1, the redundancy circuit includes a fuse unit 110 and an address comparison unit 120. The fuse unit 110 includes a fuse array 111 and a repair address output unit 113.
The fuse array 111 includes a plurality of fuses (not shown) and programs defective address information on addresses to be repaired, through a rupture operation. In this case, the fuse array 111 may be implemented with an ARE.
The repair address output unit 113 receives a reset signal RST, a mat selection signal XMATYF, and fuse data FDATA from the fuse array 111. The fuse data FDATA corresponds to the defective address information programmed into the fuse array 111.
When a boot-up operation is performed, the repair address output unit 113 sequentially receives the mat selection signal XMATYF and the fuse data FDATA corresponding to the mat selection signal XMATYF from the fuse array 111, and stores them. Thereafter, when a normal operation is performed, the repair address output unit 113 outputs data stored in response to an activated mat selection signal XMATYF, as a repair address R_ADD.
The reset signal RST is a signal for resetting the repair address R_ADD and is activated in a precharge mode. The mat selection signal XMATYF denotes a cell mat that is activated in an active operation section of a bank on which read and write operations are to be performed in a semiconductor memory device.
The address comparison unit 120 receives a normal address N_ADD from outside and the repair address R_ADD from the fuse unit 110 and outputs a redundancy enable signal RED_EN. The address comparison unit 120 compares the repair address R_ADD with the normal address N_ADD. When the repair address R_ADD is identical to the normal address N_ADD, the address comparison unit 120 activates the redundancy enable signal RED_EN for performing a repair operation on a corresponding mat.
The semiconductor memory device drives a redundancy memory cell in response to the redundancy enable signal RED_EN.
FIG. 2 is a detailed circuit diagram illustrating the repair address output unit 113 of FIG. 1.
Referring to FIG. 2, the repair address output unit 113 includes a first latch unit 2100 and a second latch unit 2200 for respectively receiving first and second mat selection signals XMATYF1 and XMATYF2.
The first and second latch units 2100 and 2200 may be implemented with a cross-coupled latch (CCL).
The first latch unit 2100 includes first to fourth storage nodes SN1 to SN4, first to fourth transistor pairs 211, 212, 213, and 214, and a driving control unit 220.
The second latch unit 2200 has the same configuration as the first latch unit 2100. The configuration and operation of the first latch unit 2100 are described as an example.
Each of the first to fourth transistor pairs 211 to 214 includes a corresponding one of PMOS transistors 211A to 214A and a corresponding one of NMOS transistors 211B to 214B, which are coupled in series through a corresponding one of the first to fourth storage nodes SN1 to SN4. Each of the storage nodes SN1 to SN4 is connected to a gate of an NMOS transistor of a transistor pair in a previous stage and a gate of a PMOS transistor of a transistor pair in a next stage. For example, the second storage node SN2 is connected to the gate of the NMOS transistor 211B of the first transistor pair 211 and the gate of the PMOS transistor 213A of the third transistor pair 213.
The driving control unit 220 includes four NMOS transistors 221 to 224. The NMOS transistors 221 to 224 are turned on in response to the first mat selection signal XMATYF1 activated to a “high” level. The driving control unit 220 transfers the fuse data FDATA received through a first data line DL1, to the first and third storage nodes SN1 and SN3, and transfers inverted fuse data FDATAB received through a second data line DL2, to the second and fourth storage nodes SN2 and SN4. Accordingly, the first and third storage nodes SN1 and SN3 and the second and fourth storage nodes SN2 and SN4 have opposite logic levels.
An operation of the first latch unit 2100 is described below.
The first to fourth storage nodes SN1 to SN4 are initially set to respective “low, high, low, and high” levels through a reset operation.
When the first mat selection signal XMATYF1 is activated to a “high” level and the fuse data FDATA of a “high” level is applied, the driving control unit 220 is activated in response to the first mat selection signal XMATYF1 of a “high” level. Accordingly, a current path is formed between the NMOS transistors 221 to 224 and the first and second data lines DL1 and DL2.
The inverted fuse data FDATAB of a “low” level is applied to the gates of the NMOS transistors 211B and 213B of the first and third transistor pairs 211 and 213 through the second data line DU, and the fuse data FDATA of a “high” level is applied to the gates of the NMOS transistors 212B and 214B of the second and fourth transistor pairs 212 and 214 through the first data line DL1. Accordingly, the first and third storage nodes SN1 and SN3 change from a “low” level to a “high” level, and the second and fourth storage to nodes SN2 and SN4 change from a “high” level to a “low” level. The first to fourth storage nodes SN1 to SN4 change to “high, low, high, and low” levels from the initially set “low, high, low, and high” levels, respectively.
In contrast, when the first mat selection signal XMATYF1 is activated to a “high” level and the fuse data FDATA of a “low” level is applied, the driving control unit 220 is activated in response to the first mat selection signal XMATYF1 of a “high” level. Accordingly, the current path is formed between the NMOS transistors 221 to 224 and the first and second data lines DL1 and DL2.
The inverted fuse data FDATAB of a “high” level is applied to the gates of the NMOS transistors 211B and 213B of the first and third transistor pairs 211 and 213 through the second data line DL2, and the fuse data FDATA of a “low” level is applied to the gates of the NMOS transistors 212B and 214B of the second and fourth transistor pairs 212 and 214 through the first data fine DL1. Accordingly, the first to fourth storage nodes SN1 to SN4 maintain the initially set “low, high, low, and high” levels regardless of the current path formed between the NMOS transistors 221 to 224 and the first and second data lines DL1 and DL2.
When a normal operation is performed, the first and second latch units 2100 and 2200 output data latched at an output node OUT through the first data line DL1 in response to the first mat selection signal XMATYF1 or the second mat selection signal XMATYF2 that is activated in response to an active command.
As a time interval tRP for which active and precharge commands are received is shortened, however, an activation section of the first mat selection signal XMATYF1 overlaps with that of the second mat selection signal XMATYF2 since the second mat selection signal XMATYF2 is activated when the activated first mat selection signal XMATYF1 has not been reset. In this case, the first latch unit 2100 and the second latch unit 2200 receive the first mat selection signal XMATYF1 and the second mat selection signal XMATYF2 at the same time. Accordingly, the driving control units 220 and 240 of the first latch unit 2100 and the second latch unit 2200 are simultaneously driven. When the driving control units 220 and 240 of the first latch unit 2100 and the second latch unit 2200 are driven at the same time, a current path between the first latch unit 2100 and the first and second data lines DL1 and DL2 and a current path between the second latch unit 2200 and the first and second data lines DL1 and DL2 are formed at the same time.
First and third storage nodes SN1 and SN3 of the second latch unit 2200 receive voltage levels of the first and third storage nodes SN1 and SN3 of the first latch unit 2100 through the first data line DL1. The first and third storage nodes SN1 and SN3 of the second latch unit 2200 change in response to the voltage of the first latch unit 2100 received through the first data line DL1. Accordingly, the data latched in the second latch unit 2200 during the boot-up operation changes during the normal operation. Thereafter, when the second mat selection signal XMATYF2 is activated, the second latch unit 2200 outputs the data changed during the normal operation, not the data latched during the boot-up operation.
Accordingly, the repair address output unit 113 outputs the data changed during the normal operation, as the repair address R_ADD. As described above, the semiconductor memory device determines whether the normal address N_ADD corresponds to a defective memory cell by comparing the repair address R_ADD received from the repair address output unit 113, with the normal address N_ADD received from the outside (e.g. an external device or host). However, the known redundancy circuit of the semiconductor memory device erroneously determines whether the normal address corresponds to the defective memory cell since it outputs the changed data as the repair address, not the latched data. Accordingly, the reliability in the repair operation of the semiconductor memory device is reduced.